Kernel MPC8270 Verification Project

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Project to track status for Kernel MPC8270 verification

Description

The project will verify that the MPC8270 is compatible with the Deos Kernel.

Minutes for Status Meetings

Status meetings



Errata Analysis Spreadsheet

Errata Analysis

Timesite Administrivia

See Timesite_Codes

Requirement Changes


The following items were listed in PCR 5287. These items will involve changes to the file ppc603e-table.sgm.

G2 Core

Finding Description Assigned To Hours Worked Completed
G2-Core-1 A new hardware implementation register, HID2, added instruction and data cache locking mechanism. Entries for HID1 and HID2 should be added to the Table of PowerPC Processor States similar to the HID0 entry. GCraig 4.0 11/03/2008
G2-Core-2 The value of MSR[IP], interrupt prefix, is determined at hard reset by the hardware configuration word. An additional comment should be added to the footnote for the IP field of the Machine State Register (MSR) in the Table of PowerPC Processor States. GCraig 2.0 11/07/2008
G2-Core-3 Removed HID0[EICE]. A footnote should be added to the Table of PowerPC Processor States documenting this fact. GCraig 1.0 11/07/2008
  • Note: These registers are also included on the G2_LE core.

G2_LE Core

Finding Description Assigned To Hours Worked Completed
G2-LE-Core-1 The MSR has a new bit field, CE. The CE bit field enables/disables the Critical Interrupt. The Table of PowerPC Processor States should state the register is cleared. GCraig 0.5 11/04/2008
G2-LE-Core-2 The registers CSRR0 and CSRR1 have been added to save the state of the processor when a Critical Interrupt (^CINT) occurs. The Table of PowerPC Processor should state these registers are cleared. GCraig 2.0 11/07/2008
G2-LE-Core-3 Additional SPRGs(SPRG4-SPRG7) have been added. The Table of PowerPC Processor States should state that these new SPRG registers should be cleared. GCraig 1.0 11/04/2008
G2-LE-Core-4 A new address breakpoint register, IABR2, has been added. The Table of PowerPC Processor States should state that the new IABR2 register should be cleared. GCraig 2.0 11/10/2008
G2-LE-Core-5 Two new data breakpoint registers, DABR1 and DABR2, have been added. The Table of PowerPC Processor States should state that the new DABR1 and DABR2 registers should be cleared. GCraig 2.0 11/10/2008
G2-LE-Core-6 One instruction register, IBCR, and one data breakpoint control register, DBCR, are implemented. The Table of PowerPC Processor States should state that the new IBCR and DBCR registers should be cleared. GCraig 2.0 11/13/2008
G2-LE-Core-7 An additional four pairs of data BAT registers (DBAT4-DBAT7) and four pairs of instruction BAT registes (IBAT4-IBAT7) have been added. These additional registers should be cleared. GCraig 2.0 11/03/2008

Test Infrastructure

Tests


Currently most tests are passing. We have to perform an initial RFS to verify that tpk028, tpk029, and tpk031 will now succeed. This initial RFS will performed Wednesday 01/07/09 in the Redmond lab area.

Reviews


Boot Code Limitations

Critical Interrupt

The MPC8270 supports a critical interrupt on IRQ5 if the proper bit is set in the MSR (Machine State Register). Deos(TM) does not support the critical interrupt because the assembly instruction rcfi has not been implemented in the Deos(TM) kernel. Therefore the Boot code written for a MPC8270 must do the following:

  • The CE bit field (bit 24 as described in Table 2-4 "MSR Bit Settings" of the "G2 PowerPC(TM) Core

Reference Manual") must be cleared. Note that is the default value when the MPC8270 processor is reset.

  • The CSSR0 register is not supported
  • The CSRR1 register is not supported


Twenty-nine (29) supervisor-level registers have been added in the G2_LE core

  1. 16 new BATs
  2. 4 new SPRGs
  3. 3 new breakpoint registers
  4. 2 instruction/Data Address breakpoint control
  5. PVR (Processor Version Register)
  6. SVR (System Version Register)
  7. MBAR System Memory Base Address
  • 16 new BATs

The following system registers, IBAT4 - IBAT7, were added to the G2_LE Core only. These are the high instruction block address translation registers available on the G2_LE Core. The high instruction block translation is used by the processor to translate virtual addresses for instruction accesses if operating in instruction address translation mode (MSR[IR]=1 and HID2[HBE]=1) and the valid bit for the current mode is set. The Deos(TM) kernel does not currently use block address translation so the valid bits (Vs,Vp) in the upper BAT of each must be set to zero. See section 2.1.2.3 of "G2 PowerPC(TM) Core Reference Manual".

  • 4 new SPRGs

Section 2.1.2.11 of of "G2 PowerPC(TM) Core Reference Manual" states that these registers are provided by the PowerPC for operating system use for purposes such as performing a fast state save or supporting microprocessor implementations. Since the Deos(TM) kernel currently does not use these registers, therefore these registers should be cleared. For information on conventional uses for SPRG4–SPRG7, refer to Section 5.2.1.3, “SPRG4–SPRG7 (G2_LE Only).”

  • debug registers, IABR and IABR2, have been added

These registers are debugging registers described in Section 2.1.2,14 "Instruction Address Breakpoint Registers (IABR and IABR2)" of "G2 PowerPC(TM) Core Reference Manual". There is no requirement to support use of these registers. The registers are never used by the Deos(TM) kernel and to eliminate the possibility of the corresponding exception (Instruction Address Breakpoint Exception) being generated these registers must be set to zero.

  • two new data breakpoint registers, DABR1 and DABR2, have been added

These are debugging registers described in Section 2.1.2.15 "Data Address Breakpoint Registers (DABR and DABR2)" of "G2 PowerPC(TM) Core Reference Manual". The registers are never used by the Deos(TM) kernel and to eliminate the possibility of the corresponding exception (DSI exception) being generated these registers must be set to zero.

  • one instruction register, IBCR, and one data breakpoint control register, DBCR, are implemented

The DBCR controls the compare and match type conditions for the DABR and DABR2 registers as described in Section 2.1.2.15.1 "Data Address Breakpoint Control Registers (DBCR)-G2_LE-Only" of "G2 PowerPC(TM) Core Reference Manual". The DABR and DABR2 registers must be enabled before the effects of the DBCR register are realized. Since the DABR and DABR2 registers are cleared, the DBCR register will have no effect.
The IBCR controls the compare and match type conditions for the IABR and IABR2 registers as described in Section 2.1.2.14.1 "Instruction Address Breakpoint Control Registers(IBCR)-G2_LE Only" of "G2 PowerPC(TM) Core Reference Manual". The IABR and IABR2 registers must be enabled before the effects of the IBCR register are realized. Since the IABR and IABR2 registers are cleared, the IBCR register will have no effect.

  • PVR (Processor Version Register) and SVR (System Version Register)

These registers are read only.

  • MBAR (System Memory Base Address)

Deos(TM) does not support this register. The reset value should not be modified.

Remaining 2009 Work

Work Item Estimated Hours Notes Completed
Official RFS 8 CMU PAL release 2.4.0.0 January 14, 2009
SQA Activity 40 Starts when Official RFS is complete
SAS 40 Last activity
Total 88


Estimated Hours To Incorporate Changes Into Mainline

File To Be Reviewed Estimated Hours
code/HAL/ppc/exception_handlers.S 16
code/HAL/ppc/halexcpt.cpp 16
code/HAL/ppc/thrd_con_arch.cpp 16
code/HAL/ppc/thrd_sup.S 16
docs/DDD/hal.sgm 16
docs/DDD/bibliography.sgm 4
docs/DDD/bootsrd.sgm 32
docs/DDD/ppc603e-table.sgm 32
RFS 80
SQA Activity 40
Total 268
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