CryptoLib

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Context

In order to enable features such as Secure Boot , a cryptographic library is needed to, at a minimal, verify cryptographic signatures.

The longer term goal is to support protocols like TLS/SSL and encrypted file systems - also see Deos Security for the Deos Security strategy.

Component Features

  • Usable from the boot loader, kernel and userspace.
  • Support for TPM2.0
  • Modular TPM transports

Status

The library is currently in experimental phase and can be found here: https://ddci.zapto.org/scm/Deos/products/crypto/experiments/branches/mainline/

Tasks

Tasks to reach MVP requirement in dependency order

ID Task Who Estimate Status Comments
1 Define high level API for verifying signatures KG 0 Done
2 Define high level API for importing keys into TPM KG 0 Done
3 Add HMAC support (required for TPM auth SHA-256 + HMAC Algo) KG 0 Done
4 Implement key importing using TSS SAPI KG 0 Done
5 Implement signature verification using TSS SAPI KG 0 Done
6 Implement TPM HAL (Infineon SLB9670XQ2.0). Requires Intel 500 PCH TIS driver KG+CC 0 Done
7 User documentation KG+CC 0 In Progress
Total @sum(column)

Tasks for generic portable CryptoLib

ID Task Who Estimate Status Comments
1 Implement MbedTLS/soft crypto based backend 0 deferred
Total @sum(column)

Algorithms

Secure Hash Algorithm SHA256/SHA512

Current implementation based on for SHA256 and for SHA512.

Benchmark

Both SHA256 and SHA512 were tested on real targets. Results are depicted in following table:

Data Size nai68int6 come-ctl6 nai68arm-2 nai68int6 come-ctl6 nai68arm-2 nai68int6 come-ctl6 nai68arm-2 nai68int6 come-ctl6 nai68arm-2 nai68int6 come-ctl6 nai68arm-2 nai68int6 come-ctl6 nai68arm-2
SHA256
1 KB 33us, 31MB/s 22us, 46MB/s 208us, 4MB/s 19us, 53MB/s 11us, 93MB/s 194us, 5MB/s 19us, 53MB/s 11us, 93MB/s 208us, 4MB/s 22us, 46MB/s 19us, 53MB/s 53us, 19MB/s 9us, 113MB/s 5us, 204MB/s 33us, 31MB/s 10us, 102MB/s 7us, 146MB/s 46us, 22MB/s
1 MB 30343us, 34MB/s 20283us, 51MB/s 199917us, 5MB/s 17129us, 61MB/s 9714us, 107MB/s 185732us, 5MB/s 17120us, 61MB/s 9746us, 107MB/s 199933us, 5MB/s 21619us, 48MB/s 15705us, 66MB/s 43485us, 24MB/s 9313us, 112MB/s 4611us, 227MB/s 29767us, 35MB/s 9286us, 112MB/s 4609us, 227MB/s 43501us, 24MB/s
4 MB 121344us, 34MB/s 81213us, 51MB/s 800100us, 5MB/s 65335us, 61MB/s 39223us, 106MB/s 743147us, 5MB/s 68309us, 61MB/s 39080us, 107MB/s 800091us, 5MB/s 86481us, 48MB/s 62696us, 66MB/s 173902us, 24MB/s 37178us, 112MB/s 18434us, 227MB/s 119186us, 35MB/s 37185us, 112MB/s 18437us, 227MB/s 173956us, 24MB/s
SHA512
1 KB 26us, 39MB/s 16us, 64MB/s 148us, 6MB/s 13us, 78MB/s 8us, 128MB/s 148us, 6MB/s 14us, 73MB/s 8us, 128MB/s 155us, 6MB/s 19us, 53MB/s 12us, 85MB/s 31us, 33MB/s 7us, 146MB/s 4us, 256MB/s 25us, 40MB/s 7us, 146MB/s 4us, 256MB/s 31us, 33MB/s
1 MB 242843us, 43MB/s 15837us, 66MB/s 131692us, 7MB/s 11382us, 92MB/s 6446us, 162MB/s 124705us, 8MB/s 11374us, 92MB/s 6433us, 162MB/s 131680us, 7MB/s 18565us, 56MB/s 12336us, 85MB/s 26001us, 40MB/s 6455us, 162MB/s 3274us, 320MB/s 18942us, 55MB/s 6425us, 163MB/s 3276us, 320MB/s 26000us, 40MB/s
4 MB 97100us, 43MB/s 63219us, 66MB/s 516576us, 7MB/s 45511us, 92MB/s 25759us, 162MB/s 498790us, 8MB/s 45514us, 92MB/s 25842us, 162MB/s 526644us, 7MB/s 74328us, 56MB/s 49352us, 84MB/s 104007us, 40MB/s 25720us, 163MB/s 13123us, 319MB/s 75806us, 55MB/s 25740us, 162MB/s 13112us, 319MB/s 104023us, 40MB/s
Configuration
Optimization Level -O0 -O0 -O0 -O2 -O2 -O2
Caching mode off writeBack writeThru off writeBack writeThru
Event Log Clock Freq 2789 2789 99 2789 2789 99 2789 2789 99 2789 2789 99 2789 2789 99 2789 2789 99

From baseline above, it is clear that the best case is -O2 writeBack caching mode. We will only track that case from now on

Data Size nai68int6 come-ctl6 nai68arm-2 nai68int6 come-ctl6 nai68arm-2
SHA256 Baseline svn rev98773
1 KB 9us, 113MB/s 5us, 204MB/s 33us, 31MB/s 9us, 113MB/s 5us, 204MB/s
1 MB 9313us, 112MB/s 4611us, 227MB/s 29767us, 35MB/s 8381us, 125MB/s 423us, 247MB/s
4 MB 37178us, 112MB/s 18434us, 227MB/s 119186us, 35MB/s 33536us, 125MB/s 16928us, 247MB/s
SHA512
1 KB 7us, 146MB/s 4us, 256MB/s 25us, 40MB/s 6us, 170MB/s 3us, 341MB/s
1 MB 6455us, 162MB/s 3274us, 320MB/s 18942us, 55MB/s 5126us, 204MB/s 2657us, 394MB/s
4 MB 25720us, 163MB/s 13123us, 319MB/s 75806us, 55MB/s 20338us, 206MB/s 10639us, 394MB/s
Configuration
Optimization Level -O2
Caching mode writeBack
Event Log Clock Freq 2789 2789 99 2789

Other material

Basic open source implementation of standard SHA256




Crystals-Dilithium

A post quantum algorithm suggested by NIST.