Deos Processor Port Notes

Here are basic notes taken when performing processor porting estimates for Deos.

Goodrich SDU Phase IV

GR contact is Barry Wolt 952-892-4009.

Basic processor requirements

• ECC
• less than 15 watts,
• decent FP unit,
• Ethernet,
• PCI express two 1x lanes,
• several USB
• SATA,
• DDR3 (preferred) DDR2 acceptable
• probably 2GB or more.

Desirements

• GPIO
• Less than 600pin package

The three processors on the GR "short list" are:

1. APM 86190 (Mamba) which uses a 465 core.
2. Freescale P2010
3. APM 460Ex

Processor Notes

Mamba

• Est part cost ~$50.
• Problem is 36-bit address space, which causes substantial Deos Cost.

Very crude hack is possible:

36-bit physical address space is sparsely populated above 0x4.0000.0000.0000.0000 which means we *could* implement an interesting 32-bit address mapping to get access to the upper 36-bit addresses so long as the GR folks don't need more than 1GB of RAM, and some other restrictions hold. The basic idea is to take a 32-bit physical address and expand it into a 36-bit address by applying some rules. Given a 32-bit address: 0xNxxx xxxx, we translate it into a physical address 0xMYxxx xxxxx converting N to MY by applying the following rules: If N is:

   0-3 DDR addresses, replace "N" by "0N" (zero N).  This would
       eliminate access to Mailboxes/DDRC Registers, not sure if
       that is acceptable.
   4   Reserved (i.e., N/A)
   5-C SATA and PCIE, hopefully we could replace N by "N0", i.e.,
       the upper 32-bit nibble in the real address would always be zero.
   D   CSR, replace "D" with "DD".  This would mean that the deep
       sleep fabric would not be accessible.
   E   OMCC (PPC boot), replace "E" with "EF" (all other E
       addresses are reserved.
   F   Replace "F" with "FA".  the NOR/NDAND/EBUS peripherals
       devices would be inaccessible (I think this means boot ROM would
       not be visible).

460EX (PPC460EX_460EXr_460GT_UM2024.pdf)

Barry says:

• Performance is weak
• Part cost is ~$60
• DDR2 w ECC.

Uses 36-bit physical addresses. Problems:

• (from https://myapm.apm.com/MyAMCC/retrieveDocument/PowerPC/PowerPC%20400%20Family/PPC440H6_464_to_PPC465_SoftwareMigration_AN4114.pdf) Cache control instructions only invalidate the L1 cache, not L2. Special L2 cache control instructions are required for L2.
  • Possible options:
    • Turn off L2 (not likely a good idea), or
    • Use L2 as fast RAM (note that on Freescale parts stwx doesn't work if L2 is all used as SRAM, not sure if the same issue is on AMCC parts or not), or
    • Indicate Bit routines don't really test RAM and don't permit "execute from flash" (i.e., we don't update Deos to flush the L2). The "Write through" bit (W) must always be set, which is not currently true in Deos.

Goodrich says they need the following onboard devices:

1. PCIe
2. DDR3 DRAM
3. GPIO
4. I2C
5. SPI
6. UART
7. Ethernet (10/100 and 1G)
8. USB
9. SATA
10. External IRQ
11. External bus for NOR Flash

Aaron searched the PPC460EX/EXr/GT Embedded processor manual revision 1.21 Dec 9, 2009) and found:

PCI references PCI0_CFGADDR which is at 0xC_0EC00000 (36-bit high nibble set).

PCIe references various registers that are offset from 0xC_10000000 (ref section 20.12.6), but it appears they can be remapped using the SDR0_PEIHS1. The other registers are DCR based (ref section 20.18 PCI Express Registers).

DDR SDRAM controller

• MQ uses DCRs (ref 22.1.1.1)
• SDRAM controller uses DCRs (ref 22.2.8.1)

GPIO uses GPIOx registers located at 0x4_EF600n00 (36-bit high nibble set). Ref Table 34-1 in section 34.4. There does not appear to be a base address register.

I2C uses registers located at 0x4_EF60n00IIC (36-bit high nibble set). Ref table 33-1 in section 33.2.

SPI uses registers located at 0x4EF6009xx (36-bit high nibble set). Ref table 39-1 in section 39.2.

UART uses registers located at 0x4EF600nxx (36-bit high nibble set). Ref table 31-2 in section 31.3.

Ethernet (EMAC) uses registers located at 0x4EF60nnxx (36-bit high nibble set). Ref section 28.10.

USB uses registers located at 0x4_BFFD0400 ( Ref table 37-2 in section 37.2.6.

SATA uses registers located at 0x4_BFFD1000 (36-bit high nibble set). Ref table 2-11 in section 2.3.3.1

I gave up at this point.

x86 Processors

They need ECC, which is first supported by core I7 (according to Barry Wolt at GR), and i7 uses too much power. This doesn't seem right to me, I thought earlier processors supported ECC RAM.

Freescale parts

P2010

Problems:

• incompatible floating point unit
• e500 kernel requirements and tests incomplete (code is done).

p4040

Uses 30watts, too much power

p3041

• 4 core, 15 watt, 1300pins
• e500mc core
• 128KB L2/core, 1MB L3 shared

Has hypervisor support. Probably means kernel changes. There is no user manual available for this processor.

Expecting part cost to be ~$200-$250.

p5010

• 1 core, 1300 pins
• core is a "5500", haven't found manual for that yet. "Intro to
• e5500 core" says it can run 32-bit code, and has classic FP.
• 512KB L2, 1MB L3
• Bary said this was too large, but he also said the 3041 might work.
• Have a phone call in to get better understanding of what he meant.

Estimates

E500MC

e500mc kernel estimates to complete (i.e., not including SPE FPU changes). Assumption here is that e500mc is the same as e500v2 with a "classic" FPU because we don't have the spec. There is some evidence that this is FALSE because the P4080 spec says it has a hypervisor. Some risk factor is warranted.

 Requirements development and review
   New section in processor tables:
     estimate 25 requirements
     2 weeks to read manual (reviewer and author)
     1.5 weeks for requirements development (3hrs/requirement)
     0.5 weeks for review
     4 weeks total    

 Code development
   1 week to finish code and do tracing

 Code review
   Estimate 12 files (the number that have 440 tags)
     50% hard(16hrs/file), 50% easy(4hrs/file): 120hrs total.
     3 weeks total

 Test development and review
   roughly 20 requirements need tests,
     5 test cases:
       2.5 days each for case and procedure development,
       1 day for review, 5*3.5~=20 days  or
       4 weeks total

 backend activities (not estimated)

e500mc would be: 12 weeks + backend

Kernel SPE FPU related changes

Kernel code and rqts changes included in "mc" estimate

 Assume compiler setup included in other estimates (for ANSI/math).
 6 existing tests have Floating point content.
   Assume 2 days each for test case and procedure development to "port" to SPE tests.
   1 day review each for test case and procedure review.
   6*3=18 days, or
   4 weeks

SPE would be: 4 weeks + 12 weeks (e500mc) + backend

Doing both SPE and MC would be an extra week or two because we were assuming "either/or" in some of the above estimates.