HotDish Boot Project

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2120-320-601; "B" Tasks
A verified Boot for the HotDish program.

Description

A verified Boot for the HotDish program.

Status

Milestones Due Date Estimated Delivery Delivered Percentage Complete
[1] HotDish Boot Full Functionality 24-MAY-10 03-MAY-10 TBD 0%
[2] HotDish Boot Verf Release 12-JUL-10 20-JUN-10 TBD 0%


[1] HotDish Boot Full Functionality

Task Dependency Assignee Original Estimate Elapsed Remaining
1.1 Design HotDish Boot None Matt, Karl 90 0 90
1.2 Implement HotDish Boot None Matt, Karl 90 0 90
1.3 Test HotDish Boot None Matt, Karl 90 0 90
1.4 Release None Matt, Karl 10 0 10
Totals 280 0 280

[2] HotDish Boot Verf Release

Task Dependency Assignee Original Estimate Elapsed Remaining
2.1 Energize Review Status Files 1.4 Matt 20 0 20
2.2 Requirements review 1.4 Matt 40 0 40
2.3 Code review 2.2 Karl 80 0 80
2.4 Test Case Development 1.4 Matt 80 0 80
2.5 Test Case Review 2.2 & 2.4 Karl 40 0 40
2.6 Test Procedure Development 1.4 Matt, Karl 100 0 100
2.7 Test Procedure Review 2.5 & 2.6 Matt, Karl 40 0 40
2.8 Software life cycle audit 2.7 Kelly 16 0 16
2.9 Requirements coverage analysis 2.7 Karl 8 0 8
2.10 Conformity inspection - SQA build Witness 2.9 Kelly, Karl 4 0 4
2.11 SCAT/ABC qualification None Matt 4 0 4
2.12 Integration review 2.10 & 2.11 Kelly, Karl 8 0 8
2.13 Run for score, including SQA witnessing, and test results review 2.12 Kelly, Karl 28 0 28
2.14 Structural coverage analysis 2.13 Matt 8 0 8
2.15 Verification audit 2.14 Kelly 8 0 8
2.16 Open Problem Reports List 2.13 Karl 16 0 16
2.17 SAS, SLCECI, SCI 2.16 Matt, Karl 4 0 4
2.18 Population of certification archive (PCA) 2.17 Matt 8 0 8
2.19 Software conformity audit 2.18 Kelly 8 0 8
Totals 520 0 520


Hotdish Boot review status summary

440 CPU_43 errata

There is an errata on the 440: CPU_43: A data-side UTLB miss might result in an erroneous data cache search parity error machine check, masking the expected TLB miss exception.

The hotdish program needs a workaround implemented. On April 18th, GR, DDC-I, and AMCC representatives got on the phone to discuss this. Of interest:

  • What can trigger the errata? e.g.,
    • Does it only happen if there is a parity error?
  • What frequency of occurrence?
    • What are factors that could affect this?
      • Temperature? Age? Radiation?
  • Can we bound the execution time?
    • Can we bound the time takes to get to the MCE after the triggering event occurs?
  • Can the triggering event be completely asynchronous?

Attendees

  • Bob Ward (AMCC?)
  • Jessie priessel (victory) local rep for AMCC
  • John Morris (Goodrich) video
  • Laurent Meilleur
  • Aaron Larson
  • Bill Cronk
  • Olga ?? Apps engineer with (I think) AMCC.
  • Grant Johnson (GR) video COE
  • Bob Ellis (GR) Safety/Reliability

The errata happens when a TLB hit is for an UNCACHED TLB entry, but the TLB still gets information regarding the cache for the associated cache block. It was not clear if the state of the cache block is an issue or not. It was stated that this is a "functional" errata, meaning that the errata is not caused by environmental conditions, but that statement was later backed away from and Olga said we'd have to have a follow on meeting to determine what the "non-functional" contributers are (otherwise this errata would happen be triggered all the time).

Olga said that the timing of the errata is essentially the same (within a few clocks) of the time when using an injected cache parity error. GR will be determining how to go about identifying the frequency of the fault and what strike counters are required.