MCFA 2023 Report

This page contains Bill's notes from attending MCFA 2023.

Notes

• Building TSN across product line working with industry groups such as Avnu
• Had 5 nano for about a month
• i.mx9 series
  • A55, NPU & M33
  • 7 - 10 watts
  • Encryption - select memory range to encrypt
• i.mx95
  • NPU has 1MB of SRAM and can be configured in SRAM mode
  • Has on-chip RAM 256kb of which is reserved for security
  • Each A55 core can run at different configured frequencies
  • A55 Can be configured to think they each have their own VPU but they don't and there is some interference. Same thing can be done with network interfaces for virtualization reasons.
  • "Roughly a thousand or so switches" that can turn unused IP on/off for power reasons
  • Pinout is same as raspberry Pi HAT
  • 'M33' is *the* core are the safety monitors and will be causing interference patterns with SW on 'A' cores
  • Cusotmers would use the M7 and leave the M33 for safety and system management
• NXP has eco system partners (e.g., engineering services)
• S32 was written to autosar standards, others not so much
• ARM
  • AE designitation on ARM 'A' cores means it has an asil safety package
  • 'R' cores all have safety packages
  • Some 'M' have saftey packages as well
  • "System Readiness" Standard for "Landing Linux"
  • Armv8.2A (A55) is a new "swim lane" or "code base" (see family tree slides)
  • 'R's are derived from cortex 'A'; micro architectural details are "brought down"
  • Cortex-R82 has an optional MMU & GIC that is shared with the 'A'
  • Architectures are developed with different requriements
  • A5x are in order A7x are ot of order execution
  • 32bit vs. 64bit is the same from a CPU prespective, compilers are different and are instructions, but the flow through a 32/64 capable processor will be the same
  • 'M' (always on) can wake up and shut down 'A'

Look into

• https://avnu.org
• Double check who has access to the MCFA share point (can email NXP Contacts for access). The 9am slide deck has access info.
• i.mx9 series NPUs
• i.mx9 safety capability
• NXP Technology Showroom
• Realtime X software (RTx from NXP)
• What would it take to support M cores?
• www.nxp.com/safeassure
• Software ecosyst (s32 presentation) has "collateral" useful for certification
• What's the legcay of the R5 relative to the A53?
• How will inline ECC affect cache partitioning, just part of the 12% peanalty?
• Safety Execution Environments and Processing Elements on the i.mx95