Zus IP Block SPI DVMS NOR MAL

SPI Based DVMS Nor MAL(s) for Ultrascale+ Based Boards. This will be used on Shire.

A DAL E project.

This page tracks development activities and progress.

Useful Links

• TBD

Meetings

2022-11-22 Assumptions to Validate

All assumptions below are from a DDP perspective. When PRP occurs, they will be revisited.

1. Confirmed: The SoC SPI based NOR Flash will be used for deosBoot.bin and hyperstart images (i.e., software images)
2. Invalid: FTP will be used to program new images into the SoC SPI based NOR Flash
   1. Xilinx tools only will be acceptable
3. Confirmed: U-Boot will be the entity responsible for moving images from SoC SPI based NOR Flash into RAM for execution
4. Confirmed: GD is aware that a switch from QSPI to SPI will cut throughput 4x
5. Confirmed: The QSPI/IP-block-SPI based NOR Flash MAL does not need a ware leveling feature
6. Confirmed: The QSPI/IP-block-SPI based NOR Flash MAL does not a bad block management feature
7. Invalid: The D4 delivery will need to be split into D4a & D4b with SoC SPI based NOR Flash capabilities first followed by the QSPI/IP-block-SPI based NOR Flash capabilities
   1. DDC-I will target the IP-block-SPI driver for D4 on 09-DEC-2022
   2. DDC-I will target the IP-block-SPI based NOR Flash interface with a single D5 release; as early as possible in January

Note: The SoC SPI based NOR Flash is configured dual-parallel, the ZUS TRM calls this:

https://docs.xilinx.com/r/en-US/ug1085-zynq-ultrascale-trm/Legacy-Quad-SPI-Dual-Slave-Select-8-bit-Parallel-I/O

ACTION on GD: Double check that Assumption #2 (see above) is truly an invalid assumption for DDP.

Activities

Task	Assignment	Status	Notes
Both Flash devices the same?	JK	Yes	SPI interfaces different (see Assumptions to Validate)
NOR MAL for IP Block based SPI	JK	Yes	Part number: Micron Technology MT25QU02GCBB8E12-0SIT