DCP BSP Fix Project

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Digital Correction Processor (DCP) is a computing platform that supports the SLS_Program.

Description

This project will modify the DCP BSP to eliminate pre-fetching on the PCI Bus. There are two proposals being considered in this quote as requested by Chris Pow.

  • Proposal 1 is for a DCP PAL only change with requirements, test test cases, and test proceedures needing to be modified to make all of flash not cachable as well as adding MFENCE instructions to the timer write function - Chris Pow will supply us with a patch file containing changes they made in their lab as a starting point.


  • Proposal 2 This would be a boot and pal change to support running the DCP using simulated flash. The boot code would also change flash to be uncachable just prior to calling the kernel entry point and then make the flash cacheable on return to boot.


News

Tasks

Budget: TBD

TTD: TBD

Current ETC: TBD

Current EAC:TBD


Delivery Due Date Estimated Delivery Delivered Percentage Complete
[1] Engineering Build Release (Date Change Note) 05/15/2009 05/18/2009 05/18/2009 100
[2] Certification Candidate Release (Date Change Note) 05/22/2009 05/22/2009 05/22/2009 100
[3] Software Accomplishment Summary Release (Date Change Note) 06/08/2009 06/10/2009 06/08/2009 100


Delivery [1] Engineering Build Release

PAL Review status summary

  • Feature Description: Requirements, code, test cases, and test procedures updated, tests run successfully on the hardware,all four classes are reviewed and accepted.

Note:: An MTRR change is user visible and as such requires a requirements update which will then require test cases and proceedures to be updated.

Task Dependency Assignee Risk Original Estimate Current Estimate Elapsed Remaining % Comp
1.0 Incorporate code changes G. Craig Johnson None Identified 8 6 6 0 100
1.1 Unofficial Review code changes Stephen Smith None Identified 1 1 1 0 100
1.2 Update requirements. G. Craig Johnson None Identified 6 6 6 0 100
1.3 Unofficial review requirements. Stephen Smith None Identified 1 1 1 0 100
1.4 Official Review requirement changes John Kimball None Identified 8 13 13 0 100
1.5 Official Review code changes John Kimball None Identified 8 13 13 0 100
1.6 Setup DCP hardware Stephen Smith Recieved corelis hardware and reflashed the box. 8 6 6 0 100
1.7 Install kernel 7.1. desk tree and verify that the pal builds and the tests run without any modifications. Uzeir Karagic None Identified 8 8 8 0 100
1.8 Engineering Build Release Uzeir Karagic None Identified 8 8 8 0 100
Totals 56 62 62 0 100



Delivery [2] Certification Candidate Release

Task Dependency Assignee Risk Original Estimate Current Estimate Elapsed Remaining % Comp
2.0 Update test cases. Miroslav Havlasek None Identified 6 6 0 6 100
2.1 Review test cases. Uzeir Karagic None Identified 6 6 6 0 100
2.2 Update test proceedures. This task includes getting all the test procedures to build and execute on the DCP platforms, and to achieve the expected structural coverage. Miroslav Havlasek None Identified 24 24 0 24 100
2.3 Review test proceedures. Uzeir Karagic None Identified 24 24 12.5 11.5 100
2.4 Rerun Test Suite Uzeir Karagic None Identified 8 8 8 0 100
2.5 Release Certification Candidate Uzeir Karagic None Identified 8 8 8 0 100
Totals 76 76 0 76 0



Delivery [3] Software Accomplishment Summary Release

  • Feature Description: Indicates all verification steps complete.
Task Dependency Assignee Risk Original Estimate Current Estimate Elapsed Remaining % Comp
3.1 Requirements coverage analysis 2.6 Uzeir Karagic 40 16 8 8 100
3.2 Conformity inspection - SQA build Witness 2.6 Stephen Smith None 8 8 1 0 100
3.3 SCAT/ABC qualification 2.6 Uzeir Karagic None 8 8 4 4 100
3.4 Integration review 2.1, 2.2, 2.3 Uzeir Karagic None 8 8 0 8 100
3.5 Run for score, including SQA witnessing, and test results review 3.4 Uzeir Karagic, Stephen Smith None 8 8 6 2 100
3.6 Structural coverage analysis 3.5 Uzeir Karagic None 8 8 4 4 100
3.7 Verification audit 3.6 Cheryl Leary None 16 16 16 0 100
3.8 Certification documents: SAS, SLCECI, SCI 2.6 John Kimball,G. Craig Johnson None 40 40 24 16 100
3.9 Population of certification archive (PCA) 2.8 Uzeir Karagic None 8 8 8 0 1000
3.10 Software conformity audit 2.9 Cheryl Leary None 16 16 8 8 100
Totals 160 136 79 50 100



Project Oversight

Task Dependency Assignee Risk Original Estimate Current Estimate Elapsed Remaining % Comp
Administrative/Project Lead G. Craig Johnson None Identified 24 24 4 20 16
2.6 Mentoring/consulting work Stephen Smith None Identified 16 16 0 16 0
Totals 40 40 4 36 10



Information about the Platform

  1. DCP does not support Power-down Look Ahead (PDLA) or warmstart. This affects quite a few decision points in the requirements for both Boot and PAL.
  2. The DCP boot has been certified once. This set of proposals are for an updaate to the PAL and optionally for the boot.

Standards

All SQA activities will be performed in compliance with: Plan for Software Aspects of Certification for Deos, DEOSDOC1 as well as all documents it references.

Organizational Responsibilities

Product Engineering

  • The project is being engineered and designed out of Minneapolis, MN. Chris Pow is the main contact. The program management contact is Kim Class.

Software Configuration Management

  • Maintain Configuration Management.
  • Maintain and Archive software requirements documents, and other associated SLCD.
  • The Honeywell Technical Lead will be responsible for this activity.

Honeywell Quality Assurance

Honeywell Program Management Responsibilities

The work responsibilities of Honeywell Program Management are as follows:

  • Facilitate the authorization of statements of work and quotes
  • Facilitate changes to statements of work
  • Provide purchase orders and payment authorization

Note: above progress should be measured against incremental, achievable tasks rather than percentage complete. Progress reports will consist of the statement that we completed a given task, didn't complete a given task (and what we will do to mitigate), or the task has changed.