DCP BSP Project
From Deos
Jump to navigationJump to search
Digital Correction Processor (DCP) is a computing platform that supports the SLS_Program.
Description
Need one here.
News
- 2007-08-02: The code is functionally complete with the exception of the HBM code which Chris Pow asked to be disabled due to a bug in the PLD. They aren't going to be fixing it for a while.
- 2007-07-12: Inital release of the BSP was made.
Tasks
Budget: $258,826
TTD: $293,768
Current ETC: $10,807
Current EAC: $304,575
| Delivery | Due Date | Estimated Delivery | Delivered | Percentage Complete |
|---|---|---|---|---|
| [1] Initial Release | 30-JUN-2007 | 06-JUL-2007 | 12-JUL-2007 | 100% |
| [2] Full Featured Release | 14-SEPT-2007 | 17-Nov-07 | 14-Nov-07 | 100% |
| [3] Certification Candidate Release (Date Change Note) | 21-DEC-2007 | 27-May-2008 | 27-May-2008 | 100% |
| [4] Software Accomplishment Summary Release (Date Change Note) | 01-MAR-2008 | 17-June-2008 | 17-June-2008 | 100% |
Date Change Note: Delivery dates changed on 4/21 due to 1) HBM PLD bug issue 2) Addition of thread timer read back change (PCR 5005).
Delivery [1] Initial Release
- Feature Description: The Deos kernel runs, the network stack pings, and files can be added and deleted from the kernel file system.
- Current Status: Done!
Delivery [2] Full Featured Release
- Feature Description: Feature complete Boot and PAL code running on DCP. PAL requirements complete. Boot requirements are partially complete
- Current Status: Done
- Note:: There is an issue with the ECC interrupt status bits not working as expected - Chris Pow is working that. The post tests are all working (The interrupt status bits that aren't working didn't keep the development of the ECC test from being completed).
| Task | Dependency | Assignee | Risk | Original Estimate | Current Estimate | Elapsed | Remaining |
|---|---|---|---|---|---|---|---|
| 2.1 Requirements Development | N/A | Stephen Smith | None identified | 120 | 144.5 | 144.5 | 0 |
| 2.2 Code Development | N/A | Stephen Smith | None identified | 500 | 453 | 453 | 0 |
| 2.3 Software life cycle audit #1 Initial audit of Boot and PAL requirements and code (2 separate audits). | 2.1, 2.2 | Kelly Leonard | None identified | 16 | 16 | 16 | 0 |
| 2.4 Software life cycle audit #2 Quarterly audit of Boot and PAL development(2 separate audits). | 2.1, 2.2 | Kelly Leonard | None identified | 0 | 16 | 10 | 0 |
| 2.5 Remove ECC setup and support from the Boot/PAL (Added by SLS on 2/11/2008) | N/A | Stephen Smith | None identified | 0 | 13 | 13 | 0 |
| Totals | 636 | 636.5 | 636.5 | 0 | |||
Delivery [3] Certification Candidate Release
- Feature Description: Sufficient verification steps complete to achieve high confidence Boot and PAL executables will not need further changes.
| Task | Dependency | Assignee | Risk | Original Estimate | Current Estimate | Elapsed | Remaining |
|---|---|---|---|---|---|---|---|
| 3.0 Requirements Development | N/A | Stephen Smith | None identified | 0 | 77 | 77 | 0 |
| 3.1 Test Development | 3.0 | 2 Belcan resources | Can we get 1 Belcan for Boot and 1 for PAL? | 600 | 1218.5 | 1218.5 | 0 |
| 3.2 Requirements review | 3.0 | Mike Horgan, Ernesto Eustaquio, Steve Pearce (GMCH/MCH sections only) | None identified | 60 | 60 | 60 | 0 |
| 3.3 Code review | 2.2 | Mike Horgan, Ernesto Eustaquio, Steve Pearce (GMCH/MCH sections only) | None identified | 250 | 208.5 | 208.5 | 0 |
| 3.4 Test review | 3.1 | 2 Belcan resources | None identified | 300 | 426.5 | 426.5 | 0 |
| 3.5 Software life cycle audit #3 | 3.2, 3.3 | Kelly Leonard | None identified | 16 | 16 | 16 | 0 |
| 3.6 Software life cycle audit #4 | 3.4 | Kelly Leonard | None identified | 16 | 16 | 16 | 0 |
| 3.7 Timer Write Readback test | 3.0 | stephen Smith, Belcan Resources | None Identified | 0 | 41.5 | 41.5 | 0 |
| Totals | 1242 | 2064 | 2064 | 0 | |||
Delivery [4] Software Accomplishment Summary Release
- Feature Description: Indicates all verification steps complete.
| Task | Dependency | Assignee | Risk | Original Estimate | Current Estimate | Elapsed | Remaining |
|---|---|---|---|---|---|---|---|
| 4.1 Requirements coverage analysis | 3.2, 3.3, 3.4 | Stephen Smith | Can we describe any current or potential roadblocks? | 40 | 2 | 2 | 0 |
| 4.2 Conformity inspection - SQA build Witness | 4.1 | Kelly Leonard | None | 8 | 8 | 8 | 0 |
| 4.3 SCAT/ABC qualification | 3.4 | Stephen Smith | None | 8 | 1 | 1 | 0 |
| 4.4 Integration review | 4.2, 4.3 | Kelly Leonard | None | 8 | 8 | 8 | 0 |
| 4.5 Run for score, including SQA witnessing, and test results review | 4.4 | Stephen Smith, Kelly Leonard | None | 8 | 8 | 8 | 0 |
| 4.6 Structural coverage analysis | 4.5 | Stephen Smith | None | 8 | 8 | 8 | 0 |
| 4.7 Verification audit | 4.6 | Kelly Leonard | None | 16 | 8 | 8 | 0 |
| 4.8 Certification documents: SAS, SLCECI, SCI | 4.6 | Stephen Smith | None | 40 | 24 | 24 | 0 |
| 4.9 Population of certification archive (PCA) | 4.8 | Stephen Smith | None | 8 | 8 | 8 | 0 |
| 4.10 Software conformity audit | 4.9 | Kelly Leonard | None | 16 | 8 | 8 | 0 |
| Totals | 160 | 83 | 83 | 0 | |||
Risks
- We are working at getting the documentation for the Intel chip set to be used for writing the Boot requirements documentation - these documents are usually under a "for your eyes only" NDA. We may need to get more than one NDA to be able to cover authoring and review activities.
Information about the Platform
- DCP does not support Power-down Look Ahead (PDLA) or warmstart. This affects quite a few decision points in the requirements for both Boot and PAL.
- DCP does not have/need/use:
- BIC buffer
- CF on IDE
- System Tick Backup Timer (SPS Update - the EPIC backup timer is the system tick timer on the DCP)
- Frame Tick
- Time Warp
- PALkernelExtensions
- PBIT Inhibit/Allow File (do PBIT on every power up)
- Module identification discretes (we're one module type -- no need to differentiate)
- ALL_VALID discrete
- Mode discretes (I reworked it so we can mess with the GeographicAddress pins [PLD] to create a Boot Deos hook for test fixtures).
Standards
All SQA activities will be performed in compliance with: Plan for Software Aspects of Certification for Deos, DEOSDOC1 as well as all documents it references.
Organizational Responsibilities
Honeywell Responsibilities
Provide project coordination within Honeywell between departments and between Honeywell and Belcan.
Product Engineering
- The project is being engineered and designed out of Minneapolis, MN. Chris Pow is the main contact. The hardware contact is Aaron Mueller.
Software Configuration Management
- Maintain Configuration Management.
- Maintain and Archive software requirements documents, and other associated SLCD.
- The Honeywell Technical Lead will be responsible for this activity.
Honeywell Quality Assurance
- The SQA Focal will perform the required audits as per the Software Quality Assurance Plan for Deos, DEOSDOC4.
- The deliverables will consist of the aforementioned SLCD.
Honeywell Program Management Responsibilities
The work responsibilities of Honeywell Program Management are as follows:
- Facilitate the authorization of statements of work and quotes
- Facilitate changes to statements of work
- Provide purchase orders and payment authorization
Belcan Corporation Responsibilities
- Belcan Corporation will provide status to Honeywell upon request.
- Progress report should be submitted to Honeywell Technical Lead at a rate to be determined by said lead.
Note: above progress should be measured against incremental, achievable tasks rather than percentage complete. Progress reports will consist of the statement that we completed a given task, didn't complete a given task (and what we will do to mitigate), or the task has changed.
